Custom MOS Capacitor Substrate Doping Resistivity Control Array
Layouts Irregular Die Geometry Binary Capacitor Arrays
HACC100S10V101: Substrate-Engineered MOS Capacitor with Binary
Arrays & Irregular Die Geometry
Tailored Substrate Doping & Resistivity Control
The HACC100S10V101 offers customization of the silicon substrate
electrical properties as a design parameter — not a fixed foundry
default. N+ or P+ doping profiles are tailored to achieve target
resistivity from 0.001 Ohm·cm (heavily doped, low series resistance
for high-Q) to 1000 Ohm·cm (lightly doped, minimized junction
capacitance for high SRF). The depletion region width under bias is
controlled by the doping profile, enabling customer-specified C-V
curve shaping: flat capacitance vs. voltage for linear
applications, or controlled C-V slope for varactor-like tuning.
Resistivity uniformity is ±5% wafer-level and ±2% within-die,
verified by PCM (Process Control Monitor) test structures on every
wafer. This level of substrate engineering is available because
HACC uses a dedicated MOS capacitor foundry process — not a
repurposed CMOS logic flow.
Custom Non-Standard Array Layouts & Irregular Die Geometry
Standard MOS capacitors are rectangular dies with a single
capacitor plate. The HACC100S10V101 breaks this constraint: custom
die aspect ratios, irregular perimeter geometries (L-shape,
T-shape, polygonal, annular), multi-cavity array patterns, and
rotated or offset pad placement are all supported. This enables
capacitor integration into non-standard hybrid circuit footprints —
fitting around existing MMICs, waveguide transitions, or thermal
management structures — without requiring a separate interposer or
PCB. The ability to produce irregular die geometries is enabled by
the HACC sawing and singulation process, which supports
customer-defined dicing street maps and non-orthogonal die
outlines.
Integrated Multi-Value Binary Capacitor Arrays
A single HACC100S10V101 die can integrate multiple capacitor values
in a binary-weighted array: 1:2:4:8 weighting across 4–8
independent capacitor blocks, with capacitance values from 5pF to
1000pF per block. Each block has its own top electrode pad and
shares a common backside connection, enabling independent or
parallel connection at the hybrid circuit level. Block-to-block
isolation exceeds 40dB at 1GHz, and the shared substrate maintains
matched temperature coefficient (TCC <30 ppm/°C) across all
blocks. This replaces multiple discrete capacitors with a single
die, reducing assembly steps, bond wire count, and hybrid circuit
footprint — while providing the design flexibility to select any
combination of values during wire bonding.
Key Specifications
| Parameter | Value |
|---|
| Capacitance | 5pF–10,000pF, binary-weighted array blocks |
| Dielectric Type | SiO₂, SiN, Al₂O₃ high-k, 50–5000Å |
| Substrate Resistivity | 0.001–1000 Ω·cm, N+/P+ tailored |
| TCC | <30 ppm/°C (NPO/COG equivalent) |
| Voltage Rating | 6.3V–200V |
| Dielectric Strength | 250% of rated, TDDB >10 years at 125°C |
| ESR | <0.1 Ω at 1 GHz |
| Top Metallization | TiW-Au, Al-metallized, AuSn pre-deposition |
| Bottom Metallization | TiW-Au, TiW-Ni-Au, AuSn, epoxy Au |
| Chip Size | 0.25*0.25mm – 5.0*5.0mm, irregular shapes |
| Operating Temperature | -55°C to +125°C |
| Delivery | Gel-Pak, waffle pack, tape-and-reel, wafer-level |
Applications
- Multi-Channel Phased Array Beamformers — binary capacitor array for
per-element tuning, single die reduces BOM
- Custom Hybrid Circuit Integration — irregular die geometry fits
around existing MMICs and transitions
- High-Precision Tuning Networks — substrate doping tailoring for
specific C-V curve requirements
- Space-Constrained SiP Modules — multi-value array eliminates
multiple discrete SLC placements
Contact us with your target capacitance values, substrate
resistivity, and die geometry requirements. Custom MOS capacitor
prototypes with binary array integration ship in 5–7 business days.